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HI1172
August 1997
6-Bit, 20 MSPS, Video A/D Converter (CMOS)
Description
HI1172 is a 6-bit, CMOS A/D converter for video use. The adoption of a 2-step parallel conversion achieves speeds of 20 MSPS minimum, 35 MSPS typical.
Features
* Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-Bit * Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS * Low Power Consumption at 20 MSPS (Typ) (Reference Current Excluded) . . . . . . . . . . . . . . .40mW * Built-In Sample and Hold Circuit * Three-State TTL Compatible Output * Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Single * Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . 4pF * Reference Impedance . . . . . . . . . . . . . . . . . . 250 (Typ)
Ordering Information
PART NUMBER HI1172JCP HI1172JCB TEMP. RANGE (oC) -20 to 75 -20 to 75 PACKAGE 16 Ld PDIP 16 Ld SOIC PKG. NO. E16.3A-S M16.2-S
Applications
* Video Digitizing * Wireless Communications
Pinout
HI1172 (PDIP, SOIC) TOP VIEW
D0 1 D1 2 D2 3 D3 4 D4 5 D5 6 CLK 7 DVSS 8 16 AVSS 15 DVDD 14 AVDD 13 VRB 12 VIN 11 VRT 10 AVDD 9 DVDD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
4102.1
4-1062
HI1172 Functional Block Diagram
REFERENCE VOLTAGE
D0 D1 D2
1 2 3
16 AVSS LOWER DATA LATCHES 15 DVDD 14 AVDD 13 VRB
LOWER ENCODER (3-BIT)
LOWER COMPARATORS WITH S/H (3-BIT)
D3 D4 D5 CLK DVSS
4 5 6 7 8
UPPER DATA LATCHES
LOWER ENCODER (3-BIT)
LOWER COMPARATORS WITH S/H (3-BIT)
12 VIN 11 VRT 10 AVDD 9 DVDD
UPPER ENCODER (3-BIT)
UPPER COMPARATORS WITH S/H (3-BIT)
CLOCK GENERATOR
Typical Application Circuit
+
-
VIN
(LSB) D0 D1 D2 D3 D4 (MSB) D5 CLK VRB VIN VRT +5V
+
C4 C3
+
C1 +5V C2
+5V
+
-
0.1
VRT VRB 0.1
+
-
4-1063
HI1172 Pin Descriptions
NUMBER 1 to 6 SYMBOL D0 to D5 EQUIVALENT CIRCUIT DESCRIPTION D0 (LSB) to D5 (MSB) Output.
D1
7
CLK
DVDD
Clock Input.
7
DVSS
8 9, 15 10, 14 11 13
DVSS DVDD AVDD VRT VRB
11 13 AVDD
Digital GND. Digital +5V. Analog +5V. Reference Voltage (Top). Reference Voltage (Bottom).
AVSS
12
VIN
AVDD
Analog Input.
12
AVSS
16
AVSS
Analog GND.
4-1064
HI1172
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage (VRT , VRB) . . . . . . . . . . . . . . . . . . . . VDD to VSS Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Output Voltage (VOH , VOL) . . . . . . . . . . . . . . . . . VDD to VSS
Operating Conditions
Supply Voltage Range, AVDD , AVSS . . . . . . . . . . . . 4.75V to 5.25V Reference Voltage, DVDD , DVSS VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9V to 5V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 4.1V VRT - VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.9V to AVDD Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Conversion Speed, fC Integral Non-Linearity Differential Non-Linearity Supply Current Reference Pin Current Analog Input (-1dB) Analog Input Capacitance
VDD = +5V, VRB = 1V, VRT = 2V, TA = 25oC SYMBOL fC EL ED IDD IREF BW CIN RREF EOT EOB VIN = 1.5V + 0.07VRMS TEST CONDITIONS VIN = 1V to 2V fIN = 1kHz Ramp fC = 20 MSPS VIN = 1V to 2V fC = 20 MSPS VIN = 1V to 2V fC = 20 MSPS NTSC Ramp Wave Input MIN 0.5 3 175 0 15 4.0 VDD = Max VIH = VDD VIL = 0V VDD = Min VOH = VDD = 0.5V VOL = 0.4V With TTL 1 Gate and 10pF Load NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS -1.1 3.7 TYP 0.3 0.3 7 4 18 4 250 -20 35 18 1.0 1.0 40 4 MAX 20 0.5 0.5 12 5.7 325 -40 55 1.0 5 5 30 UNITS MSPS LSB LSB mA mA MHz pF mV mV V V A A mA mA ns % deg ps ns
Reference Resistance (VRT to VRB) Offset Voltage
Digital Input Voltage
VIH VIL
Digital Input Current
IIH IIL
Digital Output Current
IOH IOL
Output Data Delay Differential Gain Error Differential Phase Error Aperture Jitter Sampling Delay
TDL DG DP tAJ tSD
4-1065
HI1172 Test Circuits
+V
S2
+ S1
S1 : ON IF A < B S2 : ON IF B > A
-V AHI1172 6 A>B 6 COMPARATOR A6 A1 A0 B6 B1 B0 BUFFER
"0" DVM CLK (20MHz)
"1" 6 000 * * * 00 TO 111 * * * 10
CONTROLLER
FIGURE 1. INTEGRAL NON-LINEARITY ERROR, DIFFERENTIAL NON-LINEARITY, OFFSET VOLTAGE
I
2V fC -1kHz SG 1V 1 2 NTSC SIGNAL SOURCE 40 IRE MODULATION BURST 1V -5.2V TTL fC ECL AMP VIN HI1172 ECL 620 2V -5.2V 620 SYNC DG DP 6 TTL 6 HI20201 1 10-BIT D/A CLK 2 VECTOR SCOPE HPF
ERROR RATE
COUNTER
100
IAE 0 -40 SG (CW)
FIGURE 2. MAXIMUM OPERATIONAL SPEED, DIFFERENTIAL GAIN ERROR, DIFFERENTIAL PHASE ERROR
I
2.0V 1.0V
VDD VRT VIN VRB CLK VOL GND
2.0V IOL 1.0V
VDD VRT VIN VRB CLK
IOH
+
VOH GND
+
-
-
FIGURE 3. DIGITAL OUTPUT CURRENT TEST CIRCUIT
4-1066
HI1172 Timing Diagrams
tPW1 tPW0
CLOCK ANALOG INPUT
N
N+1
N-2 N-1
N+3 N
N+4 N+1
DATA OUTPUT
N-3
N-2
tD = 18ns
FIGURE 4. TIMING CHART 1
VI (1)
VI (2)
VI (3)
VI (4)
ANALOG INPUT
EXTERNAL CLOCK
UPPER COMPARATOR BLOCK
S (1)
C (1)
S (2)
C (2)
S (3)
C (3)
S (4)
C (4)
UPPER DATA
MD (0)
MD (1)
MD (2)
MD (3)
LOWER REFERENCE VOLTAGE
RV (0)
RV (1)
RV (2)
RV (3)
LOWER COMPARATOR BLOCK A
S (1)
H (1)
C (1)
S (3)
H (3)
C (3)
LOWER DATA A
LD (-1)
LD (1)
LOWER COMPARATOR BLOCK B
H (0)
C (0)
S (2)
H (2)
C (2)
S (4)
H (4)
LOWER DATA B
LD (-2)
LD (0)
LD (2)
DIGITAL OUTPUT
OUT (-2)
OUT (-1)
OUT (0)
OUT (1)
FIGURE 5. TIMING CHART 2
4-1067
HI1172 Digital Output
Compatibility between analog input voltage and the digital output code is indicated in the chart below.
INPUT SIGNAL VOLTAGE VRT * * * * * * * * VRB DIGITAL OUTPUT CODE STEP 0 * * * 31 32 * * * 63 0 0 0 1 0 0 1 0 1 * * * 0 0 0 MSB 1 1 1 * * * 0 1 0 1 1 1 1 1 LSB 1
Notes On Operation
* VDD , VSS - To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1F set as close as possible to the pin to bypass to the respective GNDs. * Analog Input - Compared with a flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to drive with an amplifier featuring sufficient bandwidth and drive capability. When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be prevented by inserting a resistance of about 100 in series between the amplifier output and A/D input. * Clock Input - The clock line wiring should be as short as possible. Also, to avoid any interference with other signals, separate it from the other circuits. * Reference Input - Voltage between VRT to VRB is compatible with the dynamic range of the analog input. By bypassing VRT and VRB pins to GND with a capacitor of about 0.1F, stable characteristics are obtained. * Timing - Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 18ns. * About Latch Up - It is necessary that AVDD and DVDD pins to be the common source of power supply. This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.
Operation
(See Block Diagram and Waveform)
The HI1172 is a 2-step parallel system A/D converter featuring a 3-bit upper comparators group and 2 lower comparators groups of 3-bit each. The reference voltage that is equal to the voltage between VRT-VRB/8 is constantly applied to the upper 3-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower data. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart with S, H, C symbols, i.e., input sampling (auto zero) mode, input hold mode and comparison mode. The operation of respective parts is as indicated in the chart. Input voltage Vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock. simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock. Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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